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- 1. J. Appl. Phys. 100, 094108 (2006) , “The effect of interfacial layer properties on the performance of Hf-based gate stack devices”, G. Bersuker, C. S. Park, J. Barnett, P. S. Lysaght, P. D. Kirsch, C. D. Young, R. Choi, B. H. Lee, B. Foran, K. van Benthem, S. J. Pennycook, P. M. Lenahan, and J. T. RyanThe influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase in the IL dielectric constant, which correlates to an increase of the positive fixed charge density in the IL, is found to depend on the starting,... (Read more)
- 2. J. Appl. Phys. 94, 1 (2003) , “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”,We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metaloxidesemiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit... (Read more)
- 3. Appl. Phys. Lett. 80, 4753-4755 (2002) , “Characterization of S centers generated by thermal degradation in SiO2 on (100)Si”, A. Stesmans, B. Nouwen, D. Pierreux, and V. V. Afanas'evThe structural degradation of thermal SiO2 on (100)Si under isochronal vacuum annealing in the range Tan = 950 °C1250 °C was monitored by electron spin resonance (ESR) in terms of point defect creation, including... (Read more)
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Updated at 2010-07-20 16:50:39
Updated at 2010-07-20 16:50:39
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