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- 1. Microelectron. Reliability 45, 57 (2005) , “Characterization of interface defects related to negative-bias temperature instability SiON/Si<100> systems ”,Interface defects related to negative-bias temperature instability (NBTI) in an ultrathin plasma-nitrided SiON/ Si<100> system were characterized by using conductance–frequency measurements, electron-spin resonance measure- ments, and synchrotron radiation X-ray photoelectron spectroscopy. It was confirmed that NBTI is reduced by using D2-annealing instead of the usual H2-annealing. Interfacial Si dangling bonds (Pb1 and Pb0 centers) were detected in a sample subjected to negative-bias temperature stress (NBTS). Although we suggest that NBTS also generates non-Pb defects, it does not seem to generate nitrogen dangling bonds. These results show that NBTI of the plasma-nitrided SiON/Si system is predominantly due to Pb depassivation. Plasma nitridation was also found to increase the Pb1/Pb0 density ratio, modify the Pb1 defect structure, and increase the latent interface trap density by generating Si suboxides at the interface. These changes are likely to be the causes of NBTI in ultrathin plasma-nitrided SiON/Si systems. (Read more)
- 2. Appl. Phys. Lett. 82, 3677-3679 (2003) , “Interface defects responsible for negative-bias temperature instability in plasma-nitrided SiON/Si(100) systems”, Shinji Fujieda, Yoshinao Miura, and Motofumi SaitohInterface defects generated by negative-bias temperature stress (NBTS) in an ultrathin plasma- nitrided SiON/Si(100) system were characterized by using D2 annealing, conductance-frequency measurements, and electron-spin resonance measurements. D2 annealing was shown to lower... (Read more)
- 3. J. Appl. Phys. 94, 1 (2003) , “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”,We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metaloxidesemiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit... (Read more)
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Updated at 2010-07-20 16:50:39
Updated at 2010-07-20 16:50:39
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